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1. #Debugging functions and capabilities in system software verification
2. #Debugging functions and capabilities in system software software

So what do the layers of debug look like?Īt the lowest level the actual hardware itself needs to be verified and debugged.

#Debugging functions and capabilities in system software verification

All these engines, from TLM to RTL execution and the actual chip, have one unifying property – they generate the set of information necessary to enable debug, verification and validation. Now the user operates with “the real deal” at the actual target speed, but only a limited set of debug capabilities is typically embedded in silicon and exposed to the user.

#Debugging functions and capabilities in system software software

All three technologies offer different advantages regarding bring-up speed, bug turnaround and bring-up time, as well as the actual execution speed and debug insight into the hardware.Īt the end the actual chip will be used in development boards to allow final validation of software and in-system-environmental operation. Acceleration and emulation also operate at the RT-Level, as does FPGA based prototyping. Designers will use transaction-level simulation in Virtual Prototypes, and use RTL simulation for verification. So how does one go about debug, verification and validation of such a system?Īt the top of the graphic I illustrated some of the engines used for verification, validation and the actual hardware/ software debug. oOf course this includes the processor sub-systems, but complex software is likely also running on the accelerators for graphics (think CUDA programming models) as well as application accelerators for multimedia applications, not to mention digital signal processors in the system. Complex software is running on several of the components. The chip itself is then connected to real world interfaces on a printed circuit board, connecting to cellular modems, audio, video and other interfaces. The chip features multiple processor cores – including ARM big.LITTLE – and features customer specific blocks for graphics and application acceleration, high-speed, low-speed and general peripherals.Īll of the blocks are connected through a hierarchy of SoC interconnect fabrics. It shows a multi-core chip as it could be used as an application processor for phones or tables.

The layers I counted are illustrated in the graphic associated with this post. I counted seven layers, but I am sure that one may be able to arrive at a different numbers of layers of debug depending on one’s counting. This post is about hardware/software debug, and I tried to layer a set of different levels for the scope and applicability of debug. Of course I will be in trouble once this blog is posted.